SPEAKER_01 0:00

These parasitics, when it becomes a flip chip, became lesser and like it w it was important for the RF work I was doing. And flip chip saved a lot of design work because when you design the chip, it works just as is. You don't have to account for the package as much if it's a flip chip. It is the chip. So I think now there is no chip without the packaging.

SPEAKER_00 0:27

Hello everyone and welcome to another semi-doped episode. I'm Austin Lines with Chipstrat, and with me is Vic Shaker from Vic's newsletter. Hey Vic, what's going on, man?

SPEAKER_01 0:37

Um, I don't know. Are you a trillionaire yet? Because I know somebody who's going to become a trillionaire right about sometime soon. I don't know how much money he has. I'm talking about the SpaceX IPO.

SPEAKER_00 0:49

Yes, yes. It's Friday that when we're recording this, Friday, June 12th for listeners. And right now, today is SpaceX IPO day. And so Elon Musk is going to graduate to from billionaire to trillionaire.

SPEAKER_01 1:02

Uh apparently it's uh I'm not sure really how close to uh trillionary actually is. It's just too many zeros. You know, usually we record stuff uh pretty close to when we actually publish it. But um since I'm going to be traveling next week, we decided to move this up a little bit. So if you're hearing the SpaceX news and we're like, wait, wasn't that like last week? What's he even talking about? Yeah, that's because we're recording it early this time.

SPEAKER_00 1:26

Yes, totally. Yes, summer is for travel and vacations. Um, yeah, so uh trillionaire, you know, I'm just a thousandaire, so it must be nice.

SPEAKER_01 1:37

Just adding zeros, how hard can it be? Come on.

SPEAKER_00 1:39

Yeah, yeah, right? Just add a zero. That's what I'll tell my kids when you grow up. You just gotta add a couple zeros. That's your goal.

unknown 1:46

Yeah.

SPEAKER_01 1:46

Yeah, but it's it's nice though. Like um, I think it's valued at what, like 75 billion or something. This is one of the biggest IPOs in history, and so it's exciting. It's listed under the ticker SPCX. Uh so now we have this publicly traded company that does rockets, that does chips, that does AI, self-driving cars, you name it, right? And um, yeah, what's interesting uh compared to what you like we'll talk about today is uh Elon Musk's link to Terrafab project, which is closely tied with Intel, of which we'll be talking a lot about today. So it all checks out. So the SpaceX is like tangentially related to what we're talking about today, which is advanced packaging.

SPEAKER_00 2:34

You know, there's an interesting thing to Noodalon, which is like SpaceX and all its projects is like the culmination of deep tech is cool again, deep tech is valuable, right? So it's like satellites, space, internet, electromagnetic waves. Um they make their own PCBs, so fabrication, manufacturing, and then like Terrafab, and and and but but but it does go all the way up to they have XAI and they do self-driving in cars. So it does go all the way to physical AI and actually to AI. So they kind of do span the like hard tech stack all the way from atoms all the way, you know, to intelligent bits. And space. And space, and yes, the the vast universe beyond Earth, totally.

SPEAKER_01 3:19

Elon is everywhere, he's omnipresent. It's cool. I don't know. I like all these projects are technically very interesting, and like you, the way the way you put it is like, oh yeah, you're right. He's going all the way from chips all the way to space, and there's everything in between robotics and self-driving cars, and that's amazing. Like, that's a lot of cool tech in one place. That's all I have to say about it.

SPEAKER_00 3:42

Totally. Right. And then, you know, there he does the Neuralink stuff and the boring companies, so he's got his hands in all sorts of interesting stuff. But okay, we'll save Elon for uh we should give him a whole post sometime or a whole episode, you know.

SPEAKER_01 3:55

But yeah, we should do SpaceX maybe at some point. Let the IPO settle down. Yeah.

SPEAKER_00 4:00

Yeah, yeah, yeah. They'll have an earnings call, so we'll get to listen and learn a lot. And I haven't even read like the IPO prospectus or anything, but we we'll talk SpaceX sometime. But today we're gonna talk advanced packaging. But first, a quick message from our sponsor. Today's episode is sponsored by Samba Nova. If you're running inference at scale, you know the hardware trade-offs between memory capacity, chip count, and quantization. Samba Nova Cloud sidesteps these constraints entirely. You get API access to Frontier models, including full precision Deep Seek R1 at 250 tokens per second with no hardware lead times. Texas Advanced Computing Center, OVH Cloud, and Hume are already on the platform. Try it today at the Samba Nova dashboard. The link is in the show notes.

SPEAKER_01 4:46

Yeah, very important. You know, uh advanced packaging is basically what drives AHI chips these days, and it is such a bottleneck, and TSMC has been the typical provider of advanced packaging. Now we have news that like Intel is getting in some orders for their e-MIB processing, uh which is also advanced packaging, and I should just expand it right up front. Embedded multi-dye interconnect bridge, EMIB, right? That's EMIB, uh, which is a way of connecting different chips together on some kind of a substrate. We'll talk about all the differences between um what TSMC's chip on wafer on substrate is, and within chip on wafer on substrate, which we will refer to as COVAS. Uh, there are many variations and flavors of that, and so we should you know bring all those fine details to light, and then we'll talk about eMib, what's different from that, and then really at the end we should hit on uh the whole Google's commitment to e-mib technology going forward? It's very interesting. So, yeah, that'll that's going to come in the end. So stick around for that one.

SPEAKER_00 6:02

Perfect. So, friends, you might first want to start actually with advanced packaging. What does that even mean? What is advanced about packaging? And what even is not advanced packaging? What is like simple packaging? Um, so let's let's start just at the at the at the very basics. So, packaging. So, you know, we talk a lot about wafers, TSMC making wafers and making logic chips on wafers. Um, and we've talked about you know the size of these wafers and being like dinner plates, and it's these big silicon wafers, and everything gets patterned. We've talked about lithography before, but interestingly, when you think about your computer or your phone, like there's not necessarily like an exposed piece of silicon that people see, right? You the the silicon that gets made on this wafer has to get diced into individual chips, and then they need to be packaged, which is basically everything that happens to the wafer after it leaves the fab. Um, you you need connections from the dye to the outside world for power, for signals to get the heat out. You need mechanical protection, plastic or ceramic or something so that the dye actually survives the real world. So if you like break open your phone, you don't just see like this beautiful silicon thing sitting there. You've got packaging, and you know, you'd have to like cut off the packaging to actually get to the silicon. Um, so at the highest level, you know, packaging is take after like taking the wafer, dicing it up, taking individual dye, and then actually connecting them to the surrounding environment, whether it's a PCB or whatever. Um, anything else in your experience as an electrical engineer to say very high level about packaging?

SPEAKER_01 7:46

The silicon itself, actually, apart from its interconnectivity to the outside world, needs to be protected from the elements and it also needs to be protected from like electrostatic discharge and things like this. All of this means that packaging is important. You need to protect a chip inside, and while doing so, also be able to connect to it because you just can't put a piece of silicon in a phone and expect it to do anything. So the leads or the connection points into the chip are all done through packaging. So it's an essential step that has been around for a very long time, right? So the earliest simple packaging approach was wire bonding, which is just like a piece of uh metal that comes from your PCB, uh, maybe to the chip that is sitting on the PCB. It's a very crude example, but yeah, it's just a metal wire that goes up and over and connects into the chip. Uh, this has been around for a very long time, and believe me, even in the age of AI and all of this, wire bonds do exist. Okay, they're still being used for a whole variety of products because not all is advanced packaging can handle things like I don't know, power chips. Power chips require wire bonds because they need to carry a lot of current, and so this like big honking wires that are like old school still work well. So simple packaging isn't dead, it's not like something that's in the past and it's like we've forgotten about it. Oh, those were the days. No, it's still there today, which some applications require. So the other way to do the simple packaging is like you flip the chip upside down and put solder balls there, and then you put it onto a PCB, and you know you melt the solder balls a little and so that it sticks. That is the flip chip approach. That was a game changer in I'd say the 90s, because the connection distance between the chip and the external world just got a whole lot shorter. Using those wires are like so long, but if you can put a solder ball and flip the chip upside down, it was amazing. Like it changed, it blew people's minds, and it was like a revolution in packaging in the 90s because uh now performance and the parasitics, the resistances and the capacitances all got lower, and the chips could work so much better, and everybody was like, Oh, yeah, flip chip is the best, and then ultimately it comes down, you know, to you know there are variations of that in the future as it improved. They made the distance between these solder balls closer and closer and closer. So you could put like more connections into the chip. Like if you wanted to put a thousand connections into a chip, then you need these solder balls to have like a short distance between them so that you could, you know, put a lot of uh wires into the chip like that. So that became a big thing for how to make these things smaller and smaller. So that is the evolution of basically wirebonding and flip chip. So just for somebody who's never seen the world of packaging before or anything like that.

SPEAKER_00 10:40

Yes, totally. And so again, just hitting it again, you know, wire bonding. Think like the simplest thing is if someone literally, like if you're in just a lab trying to build something for a class and you had a wafer, you would probably just literally like glue it onto a PCB and then attach the wires like from the die, like you know, at the leads, the edges of the die or something to your PCB. And you can imagine that is both both very labor intensive, it's very error prone, and then you kind of have these weird, like exposed wires, and like Vic said, they're long and they have resistance, and it just feels fragile, doesn't it? And so, of course, um this flip chip is nice because now instead of having the the top of the wafer where you have to attach wires, you just turn that upside down and you just have these short direct connections. And now it's actually the back of the wafer that's kind of exposed to the elements, if you will, and and the connections are made by sandwiching these together and you have these little micro bumps. Uh, and so you have like still uh electrical conductors to sort of help you attach and connect the the die to the PCB below it. But you can just see how ultimately once you figure out how to do that with high yield and at scale, then that is a little bit less labor-intensive, more complex, but less labor intensive and also like more reliable. Um, and so, you know, but for those early decades, this the packaging is sort of like the unglamorous part, like the manufacturing, the logic chip and everything. That's like the front end of the process, and it's it's like where the value was captured and it's complicated and very capex intensive. And uh this packaging is really like mechanical assembly and even some like human assembly. Uh it's CapEx light, but it's also like lower margin, sort of lower value add. And and so actually the industry structure, you know, way back in the day, people used to manufacture their own wafers and then they used to some would do their own packaging, but eventually, actually, some of that packaging got outsourced to OSAT, which literally stands for, I think you have to double check this, outsourced semiconductor assembly, and test. So if you ever hear the word OSAT, that's what that stands for, or the the term OSAT. And these think of the companies like Amcore, ASE, Spill, Powertech, I think. Um so so the Foundry would ship finished wafers, the OSAT dice them, wirebonds or flip chips it, um, molds it, you know, puts it in its protective casing or whatever. And then usually they do the testing as well to show that the final package still works, works as as you would expect. So yeah, that's just for people like rule of thumb to know, like fabless companies design it, a foundry fabs it, and OSAT packages it. But of course, you could also have companies like Intel and IDM where they do some or all of it in-house.

SPEAKER_01 13:47

Yeah, so that's the whole uh the basic coverage of what packaging is. And this has been a very been around a very long time. As a personal anecdote, you know, even when I started working, uh I did run into a lot of the packaging guys. Those were just like uh an it seemed like it was a necessary evil. Oh yeah, we gotta send it for packaging. You know, there's nothing fancy about it. There is nothing, it's just uh grunt and boring work because you've got to make sure that the package is designed well enough so the chip can sit inside it and they do all these tests, like uh whether that it survives the heat and it survives the temperature. You know, it's like darting the i's and crossing the T's of the semiconductor world. It it did become a performance limiter at some point, even in my own uh work that I have you know uh early in my career itself, because these parasitics, when it becomes a flip chip, became lesser and like it were it was important for the RF work I was doing. Those things matter, wirebonds are still terrible. So because my work was so parasitic sensitive and RF and all that, uh it was important. And flip chip saved a lot of design work because when you design the chip, it works just as is. You don't have to account for the package as much if it's a flip chip. However, as things got more complicated, it became a part of the design process itself. It eventually became part of the chip or an extension of the chip. And throughout time, now you know if you look at all the AI chips and all that, it is the chip. There is without advanced packaging, as we would call it now, it is the chip. So I think now there is no chip without the packaging, and it's good to define now how we transition into advanced packaging, right?

SPEAKER_00 15:42

Yes, yes, totally. So if what we talked about was simple packaging, then what is advanced packaging? What puts the advanced in advanced packaging? Well, ultimately now, so the goal is always in a dream world, we would just have huge monolithic silicon chips. And because you would have like the fastest communication and the lowest latency uh between you know dies or whatever. But as we've talked about before, and we can hit on again, there's something called a reticle limit. And so you can only make silicon dyes so big. Then we've probably talked about it in the past too, and we can talk more again. There's also this concept of chiplets, which is like, wait a minute, some things don't scale when you make transistors smaller, like SRAM or maybe even like I.O. doesn't improve as much. And oh yeah, we talked about this last week on our Intel, as we talked about Clearwater Forest, where um Intel says, hey, yes, let's make the compute dies using 18A with our smallest transistors possible, but let's have other Intel 3 dyes and Intel 7 dyes for I.O. and memory and whatnot. Ultimately, those need to get connected together. Um and even if you're NVIDIA making GPUs where your GPU is the reticle limit, they make it as big as they possibly can. And they actually want even more compute, so they take two of those. With Grace Blackwell, there's two GPUs, and they actually have two huge reticle size GPU silicon die, but they want them to behave. The goal is always to can we make this behave almost as if it's still just one big piece of silicon? So that's ultimately the goal. And and you can't do that with wire bonding, and you can't really a step in the right direction would be flip chip, but ultimately can we do even better? And so advanced packaging is saying, hey, could we actually use the same semiconductor processes as the chip itself, the logic chip itself? Can we use things like deposition, etch, and lithography to actually pattern metal interconnect at like micron scale pitches instead of big old wires? And could that help us get a lower latency, smaller resistance? And going back to tau, like tau being the time delay of signals communicating, resistance times capacitance. Could we try to shrink features even with the packaging as much as possible to you know limit tau uh and and really just all make it seem as if these dies that are being stitched together are more like as if they're on one piece of silicon?

SPEAKER_01 18:27

Okay, yeah. So that's the fundamental basis for the two technologies we mentioned in the beginning, which is like TSMC's COAS and Intel's EMIB. These are technologies designed to hold multiple chips together, uh, whether they are memory like HBM and a GPU or like multiple GPUs, like you were saying, uh, on some of these other chip platforms like the Blackwells or the Rubens, they have multiple chips. And those chips are really huge chips. So since you can't make one infinitely large GPU die, you have to stay to the reticle limit, which is actually 858 millimeters squared. Uh it's a 26 millimeter by a 33 millimeter reticle. That's about as big as you can make a chip. So the GPUs are at that limit, and to make it any bigger and put more transistors and have more compute, you've got to put multiple such reticle-limited GPUs into one substrate, which we will see. I just generically call it substrate for now, and then you hook them up. You hook them up with very, very, very fine wires because the number of connections going between either the GPU to GPU or GPU to memory are way too many. There are like just an incredible number of wires. So the connection that happens between them also is not just on a single level, it's usually multiple levels. So whatever the interconnecting mechanism is underneath these chips has to support pretty complex routing that are all very finely featured, right? That is the key that makes this advanced packaging. These are not like crude traces like a PCB is, these are almost chip-level features that are being printed on substrates so that you can almost make one die an extension of the other.

SPEAKER_00 20:18

Yes, yes. You make a really good point about the wiring interconnect geometry. And so HBM3, I think it had something like 1,024 signals coming out or something. There's a lot. And you so you're obviously having to route all of these to the GPU and you're trying to do it in small dimensions. And so, yes, this it would, you know, think of it as like an ultra mini PCB, but you're you're right, you're like even as small as possible. You're wiring all this, and you're, you know, you're needing to route around things. It's it's non-trivial at this point.

SPEAKER_01 20:53

Yeah, and HBM4 took it to 2048 parallel lanes. So that's an example of why you need uh very, very fine interconnects, very fine metal lines that go between these chips on this interconnection substrate. And that has become pretty much the stronghold of maybe one company, maybe two in the world today, right? Yes. But TSMC dominates the co-wAS packaging that require is required for all AI chips today. And they are extremely capacity limited because uh there are it is actually the way TSMC does it is actually uh it's a waifer fab process. It's not something you can do in an external third-party uh factory of some kind. You need sophisticated fab equipment to be able to make these things happen. And so that's where the whole advancedness of it comes in. And that's why somebody like a TSMC who knows how to make this with high yields uh and have a long history of making chips and uh you know running a foundry comes in. And that's why not everybody can get into this game.

SPEAKER_00 22:00

Yes, yes. So this is a really interesting point. Let's talk about this for a second. It, you know, going back in history, we talked about, okay, everyone used to be their own IDM, and then eventually there were like people said, oh, let's outsource the back end of this and let these OSATs do some of the processing. And along the way, foundries came up. And so even TSMC, which was a foundry, said, we delivered the wafer and someone else can package it for us. Not huge value there. But now we're talking about advanced packaging, and it takes the same know-how as a foundry. It takes the same tooling, the same know-how. And so now all of a sudden, it's like, wait a minute, the simple packaging is still totally used, high volume, whether it's from cheap components to expensive components, but there's this advanced packaging bit, and that's actually these fabs that can make logic chips or make memory chips are actually capable of doing the advanced packaging. And so TSMC actually entered advanced packaging, you know, I think in like the late 2000s, maybe 2010s or so, where they started looking ahead and saying, oh, this advanced packaging will be a thing, and this is something we could do. So that it could actually either create a new market, if you want to think about it that way, or act, or like um maybe bookend what OSATS can do. And you know, so it's like TSMC, there's OSATS, but now there's this advanced packaging that TSMC could do again. And so TSMC started doing RD and they, you know, came up with CoAS, which we'll talk about. They also um, I think, did some early work on info integrated fan out packaging, which we're we probably won't talk about much today. Um, but I just wanted to point out that actually now OSATs are trying to say, we want to get into advanced packaging. So OSATs are trying to expand beyond the simple packaging and actually move their way into advanced packaging. So, for example, you can go listen to Amcore's earnings call and you'll hear about this because that's where a lot of the value is accruing and is going to be more and more and more important in the years going forward. So if you're a forward-thinking OSAT, you're saying, like, hey, I don't want to be left out. I actually want to try to get into the advanced packaging game too.

SPEAKER_01 24:18

Yeah, that's amazing, right? Now, what happens is that once advanced packaging has gone into a fab, and you know, these traditional OSAC packaging houses like Amcor want to get a piece of the bigger pie by going and become doing what a fab does and doing advanced packaging, you start anybody doing this now starts to run into the same limitations uh of wafer manufacturing and or chip making, right? So to put this in perspective, I think we should just quickly step back and see, okay, we spoke about the reticle limit being 858 millimeters squared. Now the H100 was already at that limit, really, right? And you mentioned that the blackwell die is basically two reticle size dice stitched into one GPU using CoAS, right? So what's the next one? Uh how many chips are we going to put in next? Like we got two already.

SPEAKER_00 25:15

Yeah, I believe for Ruben there's supposed to be four die, four GPU dies stitched together.

SPEAKER_01 25:22

So now what happens, yeah. So with the four die thing, um it starts getting complicated. Because remember that the manufacturing process for the packaging that holds these dye together is the same thing that was used for the chip itself, right? So what that means is now you couldn't make chips that are bigger than the reticle limit, which is why it was it stopped there. But now you need to make packages that are bigger than the reticle limit. Otherwise, how are we going to put two GPUs into one and stitch them together? These packages that you are running in a wafer fab process uh now need to be, let's say, two reticle sized to hold two chips, or usually more, right? Because you need to put HBM, you need to put other stuff. So maybe three. It was maybe 3.3x the reticle size that you could make. And so that somehow started becoming the limiting factor now. And the question is, how come you can make packaging substrates that are like bigger than reticle limits uh but not ICs themselves? I think I'm not entirely sure of the right answer, but I'm going to take an educated guess because these wafer fabs that run packaging substrates are actually much simpler. You don't actually make transistors. And so that means that you can probably stitch together a few reticle shots worth and make a larger reticle substrate that can hold maybe two or four GPUs at one time, right? So that's where it comes from. Uh, what do you think? Is that do you think that's the right answer as to why you can make advanced packaging that's 3x reticle size?

SPEAKER_00 27:09

Yeah, yeah. Well, which by definition, advanced packaging has to be bigger than reticle size, because like you said, you're taking reticle size like dies and you're wiring them together. So I think that's just the key, is that ultimately advanced packaging is still just drawing wires. So you're not trying to in one shot draw a bunch of tiny resistors, and you're not necessarily using this like 18A style like pitch and tools. You're using semiconductor tools, but it's still bigger. You're still drawing wires ultimately, um, like like metal wires, if you will. Um, so I think conceptually it's more about you're taking these dies and you're able to pattern, use lithography and pattern, but you're you're drawing wires. Now, I don't I don't think you're necessarily we should I I need to learn this, it's a great question. You're I don't think you're drawing all the wires in one shot, you know. So you're probably like putting the wires in over here and over there and over here and over here still, like kind of like stepping around.

SPEAKER_01 28:13

Yeah. So this whole chip on wafer on substrate or co-wash technology, and we will get right now very quickly, we're going to get into what the wafer and substrate is, but it's typically referred to as a 2.5D packaging technology. It's only 2.5 D because uh you have a uh uh active piece of silicon that is with transistors, packaged over, let's say a passive piece of silicon without transistors, but it's still silicon, right? So uh that is the chip-on-wafer process. So the chip with active elements like transistors is packaged over silicon on wafer, so chip on wafer, and that is 2.5D, right? Now if you the 3D version of this would be uh stacking a logic chip on top of a logic chip or active on active. So 2.5D is active on passive, 3D is active on active. So that is a packaging technology that is around uh in all of these fabs too, but we won't get into it too much today because that is really not an advanced packaging technique, it's a method of stacking active circuits together.

SPEAKER_00 29:27

Yes. So let me, I'm gonna say it again because it's like marking terminology and people will get weirded out by it, but this is just industry standard. So there's 2D, 2.5D, and 3D. And um, yeah, three the 3D is really cool, and we should talk about it sometime. Um stacking logic chips, but we won't talk about it a ton today, but just to define these things, because people are, you know, in your brain, you're probably thinking, like, two dimensions, I okay, I get it. Like maybe it's like a piece of paper, like the surface of it, and three dimensions, like I get that. We live in a three-dimensional world. What the heck is 2.5D? And again, just industry conventions. Sorry, semiconductor industry is weird. Just like we talked about 18A doesn't mean things are 1.8 nanometers or 18 nanometers or whatever, uh, or 18 angstroms, 1.8 nanometers. Um, that's kind of a lie. And 2.5D is also a lie, but it's just the naming convention. So engineers don't overthink this. Um, so basically, think of when we talked about um flip chip or hybrid bonding, just think of that as like 2D. Like you've got a die and you slap it on substrate and you wire it together, and just think like the die is sort of like 2D, it's just a die. Like you're looking at the surface of it, whatever. 2D. 3D is is what Vic said is the far other end of the spectrum, which is like you're trying to stack things, right? You know, this is like you're building the skyscraper, whatever. It has multiple stories, if you will. So that would be 3D. And then 2.5D is like, hey, um we're gonna increase the size of this house, but instead of building many stories, we're just gonna put a bunch of little houses next to each other, and then we're gonna like build a hallway that connects them all, right? So that so this is 2.5D. So think of like, you know, you've got a compute die and you've got another compute die, uh, like two GPUs, for example, and then you're stitching them together. That would be 2.5D. Or even technically, HBM memory connected to a GPU is also considered 2.5D, which can get a little confusing because technically, internally within HBM, it is actually 3D, it is stacked, right? Like these uh HBM can be like 12 high or 8 high or whatever. But now I'm getting way too, I'm giving you way too much information because you're probably getting confused. But but generally, when you think about 2.5D, just think that like it's one story, but it's like chips next to each other and they're connected. And like Vic said, there's a key point which is in 2.5D, and we're gonna get into the details. We're we're fine, we've buried the lead. We will finally explain to you what co-ops is, but when you connect these things, there's usually a passive interposer, as we'll talk about in 2.5D. So, okay, Vic, let's talk about chip on wafer on substrate.

SPEAKER_01 32:12

Okay, yeah, we've got to get to it, right? At some point. But all this background is important because otherwise, if we just dive right into it, co-as is this and that, it just like it loses. People who are not familiar with this stuff just like lose context immediately. And I felt it in the past, uh, and I think this background so far was useful, and I hope everybody feels the same way. But chip on wafer on substrate, okay. Chip is the GPU, right? Is sitting on a wafer. The wafer in this case could be a piece of silicon, right? It's a silicon wafer, but it doesn't have any transistors on it, it just has metal lines that can connect to another chip sitting nearby. So that's the chip on wafer. And this stack of the chip sitting on a piece of silicon now sits on top of a wafer. So it's like a three-layer stack, right? And that is what is COWOS, and that is the big thing that uh TSMC made you know go into production around the early 2010s, uh, with FPGAs, I think, initially. But it actually enabled the stitching together of multiple active pieces of silicon. Now the question is, it's obvious to ask at this point. So, why do you need this like wafer in between? Why don't you just put chip and put it on the substrate? You you've been saying you're just going to connect the chip via substrate so far. What is what is this interposer? What is this uh intermediate wafer W you talk about, what you also call an interposer sometimes, and then you also call it a piece of passive silicon wafer. Yeah, these are all these all mean the same thing actually. And um why that is required is because on a substrate, when you call it substrate, it's something like a PCB or it's something like uh a different material that's not silicon, also sometimes called organic substrates because of the kind of materials they're made of. They're made of organic materials, and so you can't pattern fine lines on them, and that's the whole problem. So that the COVAS solution was like, okay, we don't need to pattern the fine stuff on the substrate, we'll just do the core stuff on the substrate. Like maybe you only need like a couple of power lines, right, to come into the chip. Let's just make that on the substrate, right? And hook it up with the outside world. But the connections between the chips need its own separate layer, which requires a foundry class technology to connect those things together, and that's why you need a silicon interposer to connect these three two things together, and that's what the chip on wafer does.

SPEAKER_00 34:55

Yes, exactly. It's about that intermediate layers, so you can have very fine pitched routing, lots of wires, lots of signals. So TSMC started with KOAS S. So there's different flavors of KOAS, and we'll talk about three of them. And CoAS S chip on wafer on substrate with silicon interposer, which means that that middle layer of the sandwich where the routing happens is a big silicon interposer. Um, the nice thing about silicon is it's great. You can route through it really great. It has good, you know, it's it's good for um fine-pitch metal. Um and then you just have TSC, TSVs through silicon vias that come up to the chips. Um, the downside of it is that it's expensive in that now you have you're you're using silicon wafers for routing. Ideally, we would use the world supply of silicon wafers for logic, but now you're using silicon wafers for routing, and which is fine, but it can be expensive. And so naturally there's a question oh, could that intermediate layer be something cheaper? Like, do I have to have silicon or could there be something cheaper? And so there is TSMC came out with something called COAS R, where you have an organic RDL redistribution layer interposer. So here we have an acronym within an acronym, COAS R, R stands for RDL, but an organic RDL interposer. And so now this routing layer is a cheaper organic material, not necessarily the same material as a substrate, um, but a cheaper material. Um, and you can route through that. Now, if you were paying attention, you're gonna say, but Vic literally just said organic materials are not good for fine pitch routing, and that is the trade-off. Like if you have this middle layer, maybe it's ABF or something, um you can't get as fine of pitch of routing as you can with silicon. And then also there's something uh stability, dimensional stability. Um, this these organic materials they can shrink when they're heated up, they can absorb moisture, they can warp. Um, and so you can have your routing connections move around or disconnect or short circuit or whatever. And so that because you have to account for this error, that again limits how closely you can put the wires. Um, so uh chip on wafer on substrate R, so Coaz R cannot support GPU accelerators, but it can be a still a nice advanced packaging path for anything that and it could be a little bit cheaper, maybe lower end smartphones or or automotive chips or something. I'm not, I'm not sure. Um, but it's it's not what we need for um AI accelerators. And so then the question is like, okay, well, do we just have to use CoAS S with the silicon, expensive silicon, if we can't use COAS R. And the no, there's another next step from TSMC, which tries to use the best of both of those worlds. Hey, could we get the routing density of silicon, but more of the cost like the organic substrate? And this is where CoAS L comes in. L stands for local silicon bridges in an interposer. And so the idea is, hey, what if we let that middle uh section of the sandwich be the organic material that's cheap, but then wherever we and and let it route the big signals through there, like the big power signals that Vic talked about, whatever. If they don't have to be small, route them through the cheap stuff. But in the areas where we do need really dense, really finely pitched, like close, closely spaced, bunched together wires connecting, could we have silicon? And these are silicon bridges. So the idea is, and it's complicated, but this is uh just making engineering trade-offs and saying how can we get a little bit of best of both worlds? The idea is again, you have a big, cheap bulk subs organic substrate, but then in certain places you put the local little tiny silicon bridges and you route through that. So I'll pause there. Uh any thoughts on COAS L, Vic?

SPEAKER_01 39:31

Yeah, so I wanted to let you finish to go through the three kinds of KOAS because if I interrupt the flow of the trade-offs, uh, you know, it's gets very hard to follow. So that was good, actually. It's a good explanation. The one thing I wanted to mention is that the one problem with the first one, which is the COAS S on Silicon Interposer, is that uh you are essentially making uh a foundry class packaging technology, which means that the reticle slice size is inherently limited. There's only this much you can do to make really large COAS S packages because you can only make them what was it, like 3.3x the reticle sizes, something like that. Yeah, it's very difficult to go past this, and so the early early generations of accelerators did use COAS S in spite of the cost or whatever, but uh and uh it it it kind of the industry grew out of it because the chips got so much larger, it just didn't work anymore. Like then comes the COAS R that you mentioned, and I wanted to expand the word R here. You said it's RDL interposer. RDL is an acronym and acronym which stands for redistribution layer, right? And the thing with redistribution layer is it's usually a thin layer of polyamid uh dielectric, and within the polyamid dielectric, you can pattern about two or three levels of metal layers. Uh, so this is usually even in the chips I've worked with, RDL layers come in much above the chip, so it's outside the chip, really. Even you can even deposit RDL layers on top of a chip and route connections out of the chip via RDL. Okay, that's a fan out technology, it's called a fan out technology because you can take one connection and fan it out into you know greater reaches that you can't get out of a chip because chip is so small, you want to connect it to a PCB that's big, so you have to fan it out. So the redistribution layer has been around a long time. So the idea was that why don't we use spin this same polyamid onto the wafer on you know, and then make the pattern pattern on that instead, and you're not restricted by reticle sizes as much because it's a different process technology, it's not a fab-based technology, it's not that kind of lithography, so it's a different approach. So you could actually make like stuff bigger, but like you say, it is not nearly fine enough to connect AI accelerators together, so it never ended up being used for that. So the final thing was obviously, like you mentioned, the best of both worlds. You take an organic substrate, stuff that you can't make really fine connections on, but then wherever you need the connections, just between the two chips that you have to connect, you put in just the piece of silicon that you need, right? There is a very unique aspect to using these silicon bridges only where you need them, and that is now you're not restricted by radical size, even though you're using silicon interconnects between the chips, right? Because you need to make these tiny bridges of which you can get thousands in a wafer, no problem. And then you just band-aid many chips together, like connect them together with the bridges, and now you're good. And you've got like silicon class interconnect performance, but without this retical size limitations. So you have that benefit from the KOAS S world where you could connect it with this fine interconnect, but now you're like you're breaking the reticle size limitation, which is amazing, right? That's the whole point of bridges.

SPEAKER_00 43:13

Yes, totally. Yes, exactly. So conceptually, you know, zooming out, when you have KOAS S, if you want to have a ton of GPU dies stitched together, you have to have a huge piece of silicon to go under it, right? So could you have like 20 dyes? I don't know. Can you have a crazy massive piece of silicon, right? And and to Vic's point, you you have the same lithography reticles stuff. So you'd have to like step all over the place to draw all these wires. Um, but when you're talking about bridges, it's like, oh, okay, I can just have some big cheap substrate, and then I only need to take the silicon and put it just in the little areas where I'm connecting dies. And and so, like um with with CoAS L. And so, like one analogy. That came to mind to me before is like in Iowa where I live, you know, there's it's actually very, it's actually very rural. I'm sure you all know. It's mostly cornfields. And we have roads that go all over the state. There's 99 counties in Iowa, so it's kind of like a grid. And this is kind of because of the cornfields, you know, it's just like everyone gets like a square mile by mile or whatever, 40-acre type farm. So we have all these roads, um, but we would never make all of those roads asphalt or pavement. Pavement is the best driving experience, but it's also very expensive. And we're not gonna cover the state with all, especially when there's just like one random farmer that lives out there. You're not gonna like put pavement everywhere, right? So what we do is we say, okay, okay, let's put gravel everywhere. Gravel's way cheap. It's like gravel's like, so pavement would be like silicon, like it's the best, but it's expensive. And gravel is like the organic substrate where it's just like whatever, just throw it out there over the dirt to give you a little bit more traction and so it doesn't wash out, but it's cheap. Now, we don't want to, now, yes, we live in Iowa and maybe you know you call it ticks or something, but we're not gonna, we don't want gravel everywhere. So in town, we don't use gravel, we still use asphalt. So this would be like CoAS L, where it's just like use the cheap stuff to cover most of the state, the big areas that aren't as traveled and whatever. But then like by my house, I want asphalt, right? And so CoAS L. So that's my poor man's analogy to show that like you know, you can have the best of both worlds.

SPEAKER_01 45:30

Yeah, only Austin can connect corn fields and chips like this very easily. Corn chips better or worse. Corn chips are a thing, right? Corn chips, there you go. Uh yeah, that's great. Yeah, so the whole idea of putting localized interconnects actually, by the way, fun fact, didn't actually come from TSMC because it was Intel who initially developed this uh bridge concept. It was before COAS L. So there was this whole thing that you know uh TSMC copied Intel or something, and then uh there was somebody said, Oh, we should we should file a lawsuit because they copied us or something. But yeah, the EMIB predates CoAS L. And the whole idea of EMIB was that um they eliminate the silicon interposer entirely. That was the idea for EMIB, right? What uh TSMC did with CoAS L, which is local silicon interconnect, uh, was you know, after they found the same problem that they can't go to bigger and bigger chips uh or packages anymore because they're limited in size. So Intel's foresight was that okay, how about we just skip this entirely? So even today, they they skip the middle layer, they skip the interposer entirely. So they just take the chip and put it on a substrate, bam, done, like gravel road all around, no problem. And wherever required, they just put in uh these multi-dye bridges, right? Embedded. And what they actually do is they embed this thing into this substrate. So it is like I don't know, I think of you know pushing a piece of like a cracker or something into jello, you know. Yes, I feel like you're pushing some crackers into jello. That's the feeling I have when I think about EMIB, and then you hook up uh dies like this. Uh, but yeah, so the benefit of doing this is that obviously the bridges themselves are really tiny. You could make tens of thousands of them uh or at least thousand per wafer, but the the substrate itself is not limited by the reticle size because it's not even one made in a fab. The second thing is that it's not even in a circular wafer format, it is made on like square panels because if you can make these substrates on square panels, it's amazing because there's no wastage. Like if you're trying to cut out square shapes from a circle, you know, you've always got wastage. And the bigger you make this square shape that you cut out, you know, the fewer you can circles, you the fewer you can cut out from the circles. It's so much wastage, especially as packet sizes go up from the wafer. So to your original point, the silicon wafers are already uh you know difficult to come by, but then you make these gigantic packages on them and then throw out half the wafer because it's no more, it's no more useful. You know, it's like the example is like, you know, my kids when I make pancakes, my kids are always like, I want sh, I want shapes. You know, we have these like cookie-cutter shapes on pancakes. So we take them and we press them down, and it you get a deer and a squirrel and whatever, and they're like happy about it, right?

SPEAKER_00 48:44

That's awesome.

SPEAKER_01 48:45

And then uh they're like, uh, oh, but I want this squirrel and that squirrel. But there is no more pancake left for me to squeeze out a squirrel from it, right? Yeah. So now I have to make another pancake just so that I can cut out the squirrel. Uh, because the moose already took up the last pancake and I couldn't cut out a squirrel and a moose. And now I have I'm left with all these carcasses of pancakes that I end up eating. But that's exactly what happens with um with packaging, right? Like you make these packages out of wafers, but the rest, what do you do with the rest of them? You know, those are wasteful. So but if you can, now that you know you're not cutting out a moose shape on a on a package, you're cutting out rectangles. And so if you have a panel like that is already square, you can cut them out. And there's like wastage is very little. And these panels are not the size of a wafer, like 300 millimeter diameter wafers. These panels are like 500 by 500 or something like that, you know? It's much bigger than a wafer is by a factor of you know, an order of magnitude, maybe like a five, five, six times more. So it's just much, much bigger.

SPEAKER_00 49:52

Totally. And in the the point you make is very key, which is ultimately these little bridges, these they're just little rectangles. They're you think of the dye as like you know, big, big rectangles, and then a little bridge in between them is a little rectangle. And so, as we've always talked about with yield, the smaller things are, the better your yield will be intrinsically, because there's just less surface area for a random defect to pop up. So emib can actually have good yield too. So, again, zooming way back out, back to the original problem of like, oh yeah, we did wirebonding, we did flip chip, what's next? We want to draw connections between between things, and we said, oh, this the substrate's not a great place to do it. Um, Intel had the foresight to just say, oh yes, why not why not just embed little bridges into the substrate? So when you think EMIB embedded bridge, embedded bridge, that's how I just remember EMIB, um, embedded bridge, and that's all they're doing is they're just taking that little high-yield bridge that they can easily make, and um they're just embedding it down in there and connecting the die. So that would be the progression of TSMC getting to bridges, and again, so now so okay, let's say this. What's the difference then between EMIB and CoASL? As a reminder, you said both of them have bridges. And so, again, just as a reminder, CoASL is three-layer sandwich, and the bridges are in the middle, the middle layer organic material with the bridges inside of it. And EMIB is just two layers, it's just the dyes and the substrate, and those bridges are embedded into the bottom layer there. So, just like a quick reminder.

SPEAKER_01 51:32

Yeah. So uh EMIB itself has just two versions. You will see this if you look up EMIB, is like EMIB T, which means there are through silicon veers through the bridge, and this is quite important for use in AI accelerators because you do need access to power and high-speed signals through the chip. So the through silicon veers are important. So the EMIB T stands for TSV. And there's another version called EMIB M, which stands for metal insulator metal capacitors. So those are MIM capacitors. They are just basically capacitors that are built into this bridge, which are useful for like power delivery. Because whenever you put a power signal, you want to have a what is called a bypass cap, so that if there are any fluctuations, they go, they get rid of those power supply fluctuations through the capacitor. So those are the functions of bypass capacitors, they are usually quite important in power delivery. So it's very useful to have them embedded into that because you can provide a clean power signal to whatever's on the chip. So some the variant of that is eMib M actually.

SPEAKER_00 52:42

And Intel has been doing eMib for like a decade now with their own products, um, from way back in early FPGAs to uh their uh CPU SoCs, and obviously still using it now. Over time, as technology has progressed, as transitions have gotten smaller, density has increased, the routing has increased, um Intel needed to move beyond the original EMIB, and that's kind of where they came to EMIB T and EMIB M. I'm sure just solving problems with EMIB along the way and thinking, oh, there's there's better ways to improve it so that we can continue to have higher bandwidth signals, by the way, in even tighter density and smaller, smaller spaces, smaller footprint, let's say.

SPEAKER_01 53:30

Awesome. Now uh I think we should quickly, now that we've described all the technology, do you want to quickly hit upon the the value propositions of EMIB versus co-as L?

SPEAKER_00 53:40

Sure, sure. So like ultimately, like you're saying, like the pros and cons between eMib and CoAs?

SPEAKER_01 53:47

Yeah, like yeah, let's go through the pros first and then we can try to argue why EMIB is bad.

SPEAKER_00 53:54

Okay, okay, sure. So EMIB, so pros, you so you've got two layers instead of three layers. So obviously, from a cost perspective, you don't have to deal with the cost of the separate interposer, whether that's silicon or organic substrate with local silicon in it. Um that reduces process steps, that reduce reduces material costs, that reduces interposer dicing, that reduces interpose the waste that Vic talked about from interposers. Um those are some cost things that come to mind. You talked about the panel utilization, how um the embedded die can ultimately come on, it's like a geometric benefit. It could come on a rectangle panel, and then you can dice that up and have less waste.

SPEAKER_01 54:44

Uh yeah, because uh now you know that actually indirectly translates to you know capacity because not only uh is this the panels bigger, uh, but also utilization rates are very high compared to circular wafers. And on top of that, I just want to mention it briefly here. We won't really get into it, but TSMC has the idea of going what is called chip on panel on substrate. And I thought now is a good time to at least briefly mention it because they do plan to go panel level soon. Uh by soon, I mean 2028, 2029, I believe is the time frame. So they do have this uh in mind as well.

SPEAKER_00 55:26

I guess uh scalability past the reticle limit, you kind of hit on this already. Obviously, if you were gonna have like a silicon interposer and you want to make it so big so you could put like a ton of GPU dye on it, literally, it could start to get like back to what Vic was saying earlier. If we've got like a dinner plate wafer and we take like a big brick rectangle shape out of the middle of it, and that's all the bigger it can get, like you know, basically like the diameter of the um wafer, then you're going to leave all this, all that area that's like on top and on the sides and on the bottom with the curved edge that's gonna all be waste. So obviously the cost, like eMib has cost benefits even from that. And then um whereas obviously for e-mib with just the embedded bridges, you're just taking these little pieces and you can sort of imagine scaling up to very, very large um size packages. Because, like, let's say you have a three by three grid, just conceptually, of um GPU die, let's say. Well, now you just have to put little um eMib bridges in between all of them. And so you can see, like, oh, why three by three? Why not four by four? Like you can conceptually see, like as far as the embedded bridge is concerned, it's just little bridges inside dies. It sort of feels infinitely scalable. Now there are limits, of course, but but you can see how that's very scalable. And and uh then again, you know, we talk about yield already as well, which is you're just making these little small pieces. Yes, it's um there's manufacturing that has to happen, advanced packaging, obviously, that has to happen to embed those in the right place and route through them. So it's still complicated, um, but naturally, like the yield is pretty good. So those would be some pros that come to mind. But now you take the you take the other side. What are some cons of eMib?

SPEAKER_01 57:17

Yeah, the e-mib, though, though, I think the couple of arguments against it are like one, it's never proven at scale. Okay, like TSMC has run a lot of volume on um COAS. There's a lot of history with AI accelerators. All the customers are very familiar with it. There is a risk going to EMIB. Although it does look like from the last Intel earnings call, they have a lot of advanced packaging orders in already.

SPEAKER_00 57:46

So let I'm gonna push back on your pushback. Um, Intel's been using it for a decade and they ship millions of chips every year. Okay. So so so they have internally emib itself has a ton of reps. So but to put a to to put a fine point though on your argument, you could say it doesn't have a lot of experience in other people's packages.

SPEAKER_01 58:14

I see. Okay, so it's not so Nvidia has never built one with EMIB. Although I think they're considering it.

SPEAKER_00 58:21

Right, right, right, right. Folks are considering it. And so in so Intel Foundry will tell you, like, hey, um, we'll take your die, it can be from TSMC, and we will use EMIB and just do the packaging for you. So like you don't have to commit to build your GPU with Intel Foundry and do just to unlock EMIB. Like, you in fact, you can build your dyes wherever and Intel will just package it. But but yes, there isn't a lot of um examples of that yet. In theory, it should be no different than whether it's an Intel CPU that's stitched together with eMib or a uh I don't know, a Qualcomm CPU from TSMC stitched together with EMIB or an NVIDIA GPU stitched together with EMIB. In theory, it should work. But in practice or a Google TPU, yeah, which which we'll get there. But in practice, someone's got to go first at scale.

SPEAKER_01 59:15

Yeah, yeah. Um I always kept seeing this, and we posted this on the semi-dope daily newsletter we write as well, and that is that the yield of EMIB is crossing 90%. Some I read somewhere that it's 95%. So if EMIB has been shipping for that long, even internally, do they already have the yield at scale? Is e is yield something to even worry about?

SPEAKER_00 59:39

Uh I wouldn't think so. I mean, EMIB T and EMIB M are newer, and so you know, I don't know. Let me see if I have any notes somewhere. Like, it's obviously in um like Clearwater Forest. Um I'm not I don't have a note anywhere. I don't know, you know, which chip was the first to use EMIB T or EMIB M, but all the you know, Sapphire Rapids, Granite Rapids, these all used EMIB as well. So at least the original EMIB is definitely at at scale manufacturing. So the yield should be totally fine.

SPEAKER_01 1:00:14

See, that's the argument because somebody uh uh was saying I I don't know where I read it, but somebody's like, oh, if the the yield of EMIB is only 90%, that's not good enough because the packaging yield has to be 100% because you're putting a GPU on it, you're burning a whole reticles worth of two, three nanometer technology chip just for packaging. And what do you mean you can't I can't lose like one chip out of every 10 chips? That's just not acceptable. When I saw that, I was like, okay, I buy that. Nobody wants to lose one GPU out of ten GPUs just to advance packaging. So 90% isn't good enough. So then I was wondering what is TSMC's packaging yield? Is it 99%? Like you lose one in a in a in a hundred, or is it 99.9, you lose one in a thousand? You know, so I mean every process has a has a yield. I mean, nothing is 100%. So the the higher the yield, obviously the better. But I was a little surprised with all this about 90% EMIB yield. Because if you have products shipping in Intel internally, like you said, it's a good reminder now that you mention it. I just uh the dots are connecting. Why why is the EMIB uh yield 90%? I mean, is it not 99.9% already?

SPEAKER_00 1:01:26

Yeah, it it I would guess it is. I have no idea, but when I hear EMIB is 90%, then my question is which EMIB? And my question is who says that, right? Because uh some cell side reports that might report this stuff probably don't know the history of e-mib deeply and aren't thinking about it. They're probably just thinking, like, oh yeah, every new process node has a yield, everyone has to ramp from zero. So, you know, oh interesting eMib, it must have to ramp from zero. Uh, but I I I find it a little hard to believe. But it is a really interesting question that you ask, which is what is COAS S, R, and L yields from TSMC. I don't know if that's ever been published, but that would be just a nice data data point to know in the industry. Uh obviously it must be insanely high because everyone uses it. Literally everyone uses that's why that's why eMib is interesting, right? That's why there's news recently that other people are considering EMIB. Um, it's not necessarily because co-s is bad or because it's too expensive or because the the because yields are low, it's because there is only a fixed capacity of these interposers and of all that advanced packaging.

SPEAKER_01 1:02:38

And there's been a slew of uh you know news around this because uh the apparently the Google TPU order uh seems to be booking three million TPUs to be packaged with Intel EMIM. Uh and uh that's going to be like what 2028? And apparently skinix is testing EMIB uh for HPM integration as well. And um if you're talking about the Google TPUs, actually, remember it's actually going through Media Tech, who is then using EMIM. Uh MediaTech is becoming an increasing threat to Broadcom's custom ASIC model, especially with Google TPUs, and uh something to really watch out for, and that that's why in the recent earnings call and all that, uh, people realize that this uh is this this tide is shifting from Broadcom and going to MediaTech, and that's why all this Broadcom stock has been like low of late. But yeah, so it's interesting that Google through MediaTech is going through e-mib as well. And I wanted to mention one more very interesting thing that very few people actually I think pay attention to is that Intel actually has an extremely good optics process, and technically, with their ability to package this stuff, they could use EMIB and their optical engines to make some really cool CPO stuff. I'm just saying, like Intel has that ability to make CPO.

SPEAKER_00 1:04:02

Yes. We should have a podcast on it sometime. Intel has a history of optics and photonics, not well known. Some stuff has gotten sold off and whatever, but the foundry has the capabilities that opens up interesting doors in the future. Now, of course, obviously, LipBoost here, they're laser focused on customers, they're laser focused on 18AP as a better version of 18A, working toward 14A. They're trying to win customers. It seems that it's working both from a packaging perspective. Uh, hey, they have a lot of advanced packaging capacity in New Mexico. You want to do EMIB, no problem. MediaTech, you know, get your um TPUs fabricated with CSMC, send them to us, we will stitch them together, no problem. Everyone's very focused on that. All of that is good. EMIB, like the advanced packaging business is growing, and we're talking, and yeah, um uh David Zisner, the CFO, said, don't forget that's advanced packaging alone, these are these are billions of dollars worth of commitments that we're getting. So it's it's no joke. Of course, they're trying to win customers to actually build logic chips with Intel Foundry. Um, but if they have a little bit of bandwidth somewhere, if they can hire, I mean, I know they have teams already on this, but if they can, if the business can get a little bit of focus, like they ought to be um throwing their weight a little bit towards CPO, optics, photonics. Can they make lasers? Can they take buy lasers and package them? We have to go into exactly what their capabilities are, but yeah, it could be a really interesting opportunity for Intel Foundry.

SPEAKER_01 1:05:39

Absolutely. And so just in terms of sizes, I think we should just quickly summarize where we are right now because the first generation of KOAS was like a 3.3x reticle size. Uh, I think currently the Blackwell Ultra class and the Ruben class chips are all like at the 5.5x reticle packaging that TSMC CoAS is capable of today. The next generation that is planned, I believe, will take it to 9.5x reticle size. Um that should be about it, and then they start talking about what is called a system on wafer, which uh targets something like 40x. Um I'm not sure when that is gonna come out or anything, but even uh the 7x thing is not, I think towards the latter half of uh next few years anyway.

SPEAKER_00 1:06:31

Totally, yeah, it'll make for good launch events, you know, instead of holding up the it used to be hold up a chip, and now it's like hold up an SOC, and eventually they're gonna hold up like this, you know, 7x big thing, and then someday, maybe when our kids are doing this, you know, are they holding up whole wafers? I mean cerebrus is already, yeah, yeah, cerebrus is one. And maybe C O P O S Cops or whatever would would circumvent needing system on a wafer. I don't know. We'll save that for another episode.

SPEAKER_01 1:07:00

Yeah, yeah, yeah. We are not gonna do that. But what is the size of uh EMIB panel, EMIB right now? Like what is the biggest reticle they can do?

SPEAKER_00 1:07:07

Yeah, I don't know what it is today. I know that they're going to um I think with EMIB T they're gonna get to 8x reticle size. Maybe that's where they're at today. Um, 8x reticle size. And then I think in just two years, they're gonna get to greater than 12x reticle size by 2028. And it's rectangular, like 120 by 180. If you go Google it, it's cool because you'll see they they'll show like a 2x4 grid of dies, and then all these little like rectangles that are the bridges to kind of can conceptually show you how the bridges are connecting essentially on the perimeter of all the dye and then in between all the dyes. So your two by four grid, you can picture all these little bridges on the outside connecting to other things, maybe HBM or whatever, and then also in between them, like stitching them together, so to speak. Um, so yes, uh CoAS is good, eMib also good. They have their pros and cons. I hope you learned a lot about packaging, about advanced packaging, about co-as and eMib. And thank you for listening. Um, thank you to everyone who's listening on yes, yes, very long episode. Um, maybe we'll edit it down a tiny bit. We'll see. But uh hope you enjoyed this. And uh to our YouTube listeners, thank you so much. We had so many YouTube listeners listen to our last one on tau scaling. We had tons of comments, tons of engagement. Really appreciate that. We read all of them. Um, it's it's super enlightening and it's just fun to see you guys learning and engaging. Thanks for everyone who downloads the podcast and shares it with their friends. Uh, people who watch on X, also cool. Um, good luck with the SpaceX IPO. And uh that's it. So if you're enjoying Semi Dope, share it with your friends. Subscribe to our newsletters. If you like us, we have little takes daily at semidope.com. It's totally free. Check it out, share it with your friends as well. And with that, we'll wrap it here.